1. Technical Field
Embodiments of the present disclosure relate generally to digital demodulation, and more specifically to digital demodulation of pulse-width modulated signals.
2. Related Art
Pulse width modulation (PWM) refers to a modulation technique in which data/information is embedded in (or represented by) the duty cycle of a signal. Successive periods of the signal may be concatenated to form a continuous stream of periods, with the duty cycle of each period representing corresponding data/information. The ratio of the ON (or high) duration of the signal to the period of the signal is termed duty cycle. A duty cycle of 50% corresponds to a situation when the ON and OFF durations of the signal are equal. Assuming the data modulated on the PWM signal is binary, a duty cycle less than 50% may be used to represent one value of the (binary) data, while a duty cycle greater than 50% may be used represent the other value of the data.
Digital demodulation of a PWM signal refers to extracting the modulated data from (each period of) the PWM signal using digital techniques and using only digital circuitry. One prior approach to PWM demodulation employs analog techniques to charge and discharge capacitors during high and low times respectively of a PWM input, followed by voltage comparisons. However, such an approach may be complex in terms of design effort and circuit layout, and may not be easily scalable with respect to frequency of the PWM signal. Another prior approach employs a counter operated with a very high speed clock, and counting the number of clock cycles contained in high and low durations of a PWM signal. Such an approach may not be desirable at least due to the need for a very high frequency clock (e.g., of the order of GigaHertz).